secded_codec

extras/secded_codec.vhdl

Description

This package provides a component that implements SECDED EDAC as a single unified codec. The codec can switch between encoding and decoding on each clock cycle with a minimum latency of two clock cycles through the input and output registers. The SECDED logic is capable of correcting single-bit errors and detecting double-bit errors.

Optional pipelining is available to reduce the maximum delay through the internal logic. To be effective, you must activate the retiming feature of the synthesis tool being used. See the notes in pipelining for more information on how to accomplish this. The pipelining is controlled with the PIPELINE_STAGES generic. A value of 0 will disable pipelining.

To facilitate testing, the codec includes an error generator that can insert single-bit and double-bit errors into the encoded output. When active, successive bits are flipped on each clock cycle. This feature provides for the testing of error handling logic in the decoding process.

Constants

secded_codec_pkg.CODEC_ENCODE

Select encoding mode

secded_codec_pkg.CODEC_DECODE

Select decoding mode

secded_codec_pkg.INSERT_NONE

No error injection

secded_codec_pkg.INSERT_SINGLE

Single-bit error injection

secded_codec_pkg.INSERT_DOUBLE

Double-bit error injection

Components

secded_codec

component secded_codec is generic ( DATA_SIZE : positive; PIPELINE_STAGES : natural; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Codec_mode : in std_ulogic; Insert_error : in std_ulogic_vector(1 downto 0); --# {{data|Encoding port}} Data : in std_ulogic_vector(DATA_SIZE-1 downto 0); Encoded_data : out ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right); --# {{Decoding port}} Ecc_data : in ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right); Decoded_data : out std_ulogic_vector(DATA_SIZE-1 downto 0); --# {{Error flags}} Single_bit_error : out std_ulogic; Double_bit_error : out std_ulogic ); end component;

secded_codec_pkg.secded_codec
Generics:
  • DATA_SIZE (positive) – Size of the Data input
  • PIPELINE_STAGES (natural) – Number of pipeline stages appended to end
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Codec_mode (in std_ulogic) – OPerating mode: ‘0’ = encode, ‘1’ = decode
  • Insert_error (in std_ulogic_vector(1 downto 0)) – Error injection
  • Data (in std_ulogic_vector(DATA_SIZE-1 downto 0)) – Data to encode
  • Encoded_data (out ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right)) – Data message with SECDED parity
  • Ecc_data (in ecc_vector(DATA_SIZE-1 downto secded_indices(DATA_SIZE).right)) – Received data
  • Decoded_data (out std_ulogic_vector(DATA_SIZE-1 downto 0)) – Received data with errors corrected
  • Single_bit_error (out std_ulogic) – ‘1’ when a single-bit error is detected (automatically corrected)
  • Double_bit_error (out std_ulogic) – ‘1’ when a double-bit error is detected