pipelining

extras/pipelining.vhdl

extras_2008/pipelining_2008.vhdl

Dependencies

common_2008 (for pipelining_2008)

Description

This package provides configurable shift register components intended to be used as placeholders for register retiming during synthesis. These components can be placed after a section of combinational logic. With retiming activated in the synesis tool, the flip-flops will be distributed through the combinational logic to balance delays. The number of pipeline stages is controlled with the PIPELINE_STAGES generic.

There are also components for general purpose delay lines with a fixed or variable number of stages. The VHDL-2008 package has a special tapped_delay_line component that presents all stage outputs at once.

Retiming

Here are notes on how to activate retiming in various synthesis tools:

Xilinx ISE
register_balancing attributes are implemented in the design. In Project|Design Goals & Strategies set the Design Goal to “Timing Performance”. The generic ATTR_REG_BALANCING is avaiable on each entity to control the direction of register balancing. Valid values are “yes”, “no”, “forward”, and “backward”. If the pipeline stages connect directly to I/O then set the strategy to “Performance without IOB packing”.
Xilinx Vivado
phys_opt_design -retime
Synplify Pro
syn_allow_retiming attributes are implemented in the design
Altera Quartus II
Enable “Perform register retiming” in Assignments|Settings|Physical Synthesis Optimizations
Synopsys Design Compiler
Use the optimize_registers command
Synopsys DC Ultra
Same as DC or use set_optimize_registers in conjunction with compile_ultra -retime

Components

pipeline_ul

component pipeline_ul is generic ( PIPELINE_STAGES : positive; ATTR_REG_BALANCING : string; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Sig_in : in std_ulogic; Sig_out : out std_ulogic ); end component;

pipelining.pipeline_ul

Pipeline registers for std_ulogic and std_logic.

Generics:
  • PIPELINE_STAGES (positive) – Number of pipeline stages to insert
  • ATTR_REG_BALANCING (string) – Control propagation direction (Xilinx only)
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Sig_in (in std_ulogic) – Signal from block to be pipelined
  • Sig_out (out std_ulogic) – Pipelined result

pipeline_sulv

component pipeline_sulv is generic ( PIPELINE_STAGES : positive; ATTR_REG_BALANCING : string; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Sig_in : in std_ulogic_vector; Sig_out : out std_ulogic_vector ); end component;

pipelining.pipeline_sulv

Pipeline registers for std_ulogic_vector.

Generics:
  • PIPELINE_STAGES (positive) – Number of pipeline stages to insert
  • ATTR_REG_BALANCING (string) – Control propagation direction (Xilinx only)
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Sig_in (in std_ulogic_vector) – Signal from block to be pipelined
  • Sig_out (out std_ulogic_vector) – Pipelined result

pipeline_slv

component pipeline_slv is generic ( PIPELINE_STAGES : positive; ATTR_REG_BALANCING : string; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Sig_in : in std_logic_vector; Sig_out : out std_logic_vector ); end component;

pipelining.pipeline_slv

Pipeline registers for std_logic_vector.

Generics:
  • PIPELINE_STAGES (positive) – Number of pipeline stages to insert
  • ATTR_REG_BALANCING (string) – Control propagation direction (Xilinx only)
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Sig_in (in std_logic_vector) – Signal from block to be pipelined
  • Sig_out (out std_logic_vector) – Pipelined result

pipeline_u

component pipeline_u is generic ( PIPELINE_STAGES : positive; ATTR_REG_BALANCING : string; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Sig_in : in unsigned; Sig_out : out unsigned ); end component;

pipelining.pipeline_u

Pipeline registers for unsigned.

Generics:
  • PIPELINE_STAGES (positive) – Number of pipeline stages to insert
  • ATTR_REG_BALANCING (string) – Control propagation direction (Xilinx only)
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – None
  • Sig_in (in unsigned) – Signal from block to be pipelined
  • Sig_out (out unsigned) – Pipelined result

pipeline_s

component pipeline_s is generic ( PIPELINE_STAGES : positive; ATTR_REG_BALANCING : string; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Sig_in : in signed; Sig_out : out signed ); end component;

pipelining.pipeline_s

Pipeline registers for signed.

Generics:
  • PIPELINE_STAGES (positive) – Number of pipeline stages to insert
  • ATTR_REG_BALANCING (string) – Control propagation direction (Xilinx only)
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Sig_in (in signed) – Signal from block to be pipelined
  • Sig_out (out signed) – Pipelined result

fixed_delay_line

component fixed_delay_line is generic ( STAGES : natural ); port ( --# {{clocks|}} Clock : in std_ulogic; --# {{control|}} Enable : in std_ulogic; --# {{data|}} Data_in : in std_ulogic; Data_out : out std_ulogic ); end component;

pipelining.fixed_delay_line

Fixed delay line for std_ulogic data.

Generics:
  • STAGES (natural) – Number of delay stages (0 for short circuit)
Port:
  • Clock (in std_ulogic) – System clock
  • Enable (in std_ulogic) – Synchronous enable
  • Data_in (in std_ulogic) – Input data
  • Data_out (out std_ulogic) – Delayed output data

fixed_delay_line_sulv

component fixed_delay_line_sulv is generic ( STAGES : natural ); port ( --# {{clocks|}} Clock : in std_ulogic; --# {{control|}} Enable : in std_ulogic; --# {{data|}} Data_in : in std_ulogic_vector; Data_out : out std_ulogic_vector ); end component;

pipelining.fixed_delay_line_sulv

Fixed delay line for std_ulogic_vector data.

Generics:
  • STAGES (natural) – Number of delay stages (0 for short circuit)
Port:
  • Clock (in std_ulogic) – System clock
  • Enable (in std_ulogic) – Synchronous enable
  • Data_in (in std_ulogic_vector) – Input data
  • Data_out (out std_ulogic_vector) – Delayed output data

fixed_delay_line_signed

component fixed_delay_line_signed is generic ( STAGES : natural ); port ( --# {{clocks|}} Clock : in std_ulogic; --# {{control|}} Enable : in std_ulogic; --# {{data|}} Data_in : in signed; Data_out : out signed ); end component;

pipelining.fixed_delay_line_signed

Fixed delay line for signed data.

Generics:
  • STAGES (natural) – Number of delay stages (0 for short circuit)
Port:
  • Clock (in std_ulogic) – System clock
  • Enable (in std_ulogic) – Synchronous enable
  • Data_in (in signed) – Input data
  • Data_out (out signed) – Delayed output data

fixed_delay_line_unsigned

component fixed_delay_line_unsigned is generic ( STAGES : natural ); port ( --# {{clocks|}} Clock : in std_ulogic; --# {{control|}} Enable : in std_ulogic; --# {{data|}} Data_in : in unsigned; Data_out : out unsigned ); end component;

pipelining.fixed_delay_line_unsigned

Fixed delay line for unsigned data.

Generics:
  • STAGES (natural) – Number of delay stages (0 for short circuit)
Port:
  • Clock (in std_ulogic) – System clock
  • Enable (in std_ulogic) – Synchronous enable
  • Data_in (in unsigned) – Input data
  • Data_out (out unsigned) – Delayed output data

dynamic_delay_line_sulv

component dynamic_delay_line_sulv is port ( --# {{clocks|}} Clock : in std_ulogic; --# {{control|}} Enable : in std_ulogic; Address : in unsigned; --# {{data|}} Data_in : in std_ulogic_vector; Data_out : out std_ulogic_vector ); end component;

pipelining.dynamic_delay_line_sulv

Fixed delay line for std_ulogic_vector data.

Port:
  • Clock (in std_ulogic) – System clock
  • Enable (in std_ulogic) – Synchronous enable
  • Address (in unsigned) – Selected delay stage
  • Data_in (in std_ulogic_vector) – Input data
  • Data_out (out std_ulogic_vector) – Delayed output data

dynamic_delay_line_signed

component dynamic_delay_line_signed is port ( --# {{clocks|}} Clock : in std_ulogic; --# {{control|}} Enable : in std_ulogic; Address : in unsigned; --# {{data|}} Data_in : in signed; Data_out : out signed ); end component;

pipelining.dynamic_delay_line_signed

Fixed delay line for signed data.

Port:
  • Clock (in std_ulogic) – System clock
  • Enable (in std_ulogic) – Synchronous enable
  • Address (in unsigned) – Selected delay stage
  • Data_in (in signed) – Input data
  • Data_out (out signed) – Delayed output data

dynamic_delay_line_unsigned

component dynamic_delay_line_unsigned is port ( --# {{clocks|}} Clock : in std_ulogic; --# {{control|}} Enable : in std_ulogic; Address : in unsigned; --# {{data|}} Data_in : in unsigned; Data_out : out unsigned ); end component;

pipelining.dynamic_delay_line_unsigned

Fixed delay line for unsigned data.

Port:
  • Clock (in std_ulogic) – System clock
  • Enable (in std_ulogic) – Synchronous enable
  • Address (in unsigned) – Selected delay stage
  • Data_in (in unsigned) – Input data
  • Data_out (out unsigned) – Delayed output data

VHDL-2008 variant

Components

tapped_delay_line

component tapped_delay_line is generic ( RESET_ACTIVE_LEVEL : std_ulogic; REGISTER_FIRST_STAGE : boolean ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Enable : in std_ulogic; --# {{data|}} Data : in std_ulogic_vector; Taps : out sulv_array ); end component;

pipelining.tapped_delay_line

Vector delay line with an output for each stage.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
  • REGISTER_FIRST_STAGE (boolean) – Register or pass through the first stage
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Enable (in std_ulogic) – Enable delay line
  • Data (in std_ulogic_vector) – Input to the delay line
  • Taps (out sulv_array) – Taps from each stage