glitch_filtering

extras/glitch_filtering.vhdl

Dependencies

sizing

Description

This package provides glitch filter components that can be used to remove noise from digital input signals. This can be useful for debouncing switches directly connected to a device. The glitch_filter component works with a single std_ulogic signal while array_glitch_filter provides filtering for a std_ulogic_vector. These components include synchronizing flip-flops and can be directly tied to input pads.

It is assumed that the signal being recovered changes relatively slowly compared to the clock period. These filters come in two forms. One is controlled by a generic FILTER_CYCLES and the other dynamic versions (dynamic_glitch_filter and dynamic_array_glitch_filter) have a port signal Filter_cycles. These controls indicate the number of clock cycles the input(s) must remain stable before the filtered output register(s) are updated. The filtered output will lag the inputs by Filter_cycles + 3 clock cycles. The dynamic versions can have their filter delay changed at any time if their Filter_cycles input is connected to a signal. The minimum pulse width that will pass through the filter will be Filter_cycles + 1 clock cycles wide.

Example usage

library extras;
use extras.glitch_filtering.all; use extras.timing_ops.all;
...
constant CLOCK_FREQ    : frequency    := 100 MHz;
constant FILTER_TIME   : delay_length := 200 ns;
constant FILTER_CYCLES : clock_cycles :=
  to_clock_cycles(FILTER_TIME, CLOCK_FREQ);
...
gf: glitch_filter
  generic map (
    FILTER_CYCLES => FILTER_CYCLES
  ) port map (
    Clock    => clock,
    Reset    => reset,
    Noisy    => noisy,
    Filtered => filtered
  );

Xilinx XST doesn’t support user defined physical types so the frequency type from timing_ops.vhdl can’t be used with that synthesizer. An alternate solution using XST-compatible timing_ops_xilinx.vhdl follows:

constant CLOCK_FREQ    : real         := 100.0e6; -- Using real in place of frequency
constant FILTER_TIME   : delay_length := 200 ns;
constant FILTER_CYCLES : clock_cycles :=
  to_clock_cycles(FILTER_TIME, CLOCK_FREQ)
...

Components

glitch_filter

component glitch_filter is generic ( FILTER_CYCLES : positive; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Noisy : in std_ulogic; Filtered : out std_ulogic ); end component;

glitch_filtering.glitch_filter

Basic glitch filter with a constant filter delay This version filters a single signal of std_ulogic

Generics:
  • FILTER_CYCLES (positive) – Number of clock cycles to filter
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Noisy (in std_ulogic) – Noisy input signal
  • Filtered (out std_ulogic) – Filtered output

dynamic_glitch_filter

component dynamic_glitch_filter is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Filter_cycles : in unsigned; --# {{data|}} Noisy : in std_ulogic; Filtered : out std_ulogic ); end component;

glitch_filtering.dynamic_glitch_filter

Glitch filter with a dynamically alterable filter delay This version filters a single signal of std_ulogic component dynamic_glitch_filter is

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Filter_cycles (in unsigned) – Number of clock cycles to filter
  • Noisy (in std_ulogic) – Noisy input signal
  • Filtered (out std_ulogic) – Filtered output

array_glitch_filter

component array_glitch_filter is generic ( FILTER_CYCLES : positive; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Noisy : in std_ulogic_vector; Filtered : out std_ulogic_vector ); end component;

glitch_filtering.array_glitch_filter

Basic glitch filter with a constant filter delay This version filters an array of std_ulogic

Generics:
  • FILTER_CYCLES (positive) – Number of clock cycles to filter
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Noisy (in std_ulogic_vector) – Noisy input signals
  • Filtered (out std_ulogic_vector) – Filtered output

dynamic_array_glitch_filter

component dynamic_array_glitch_filter is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Filter_cycles : in unsigned; --# {{data|}} Noisy : in std_ulogic_vector; Filtered : out std_ulogic_vector ); end component;

glitch_filtering.dynamic_array_glitch_filter

Glitch filter with a dynamically alterable filter delay This version filters an array of std_ulogic

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Filter_cycles (in unsigned) – Number of clock cycles to filter
  • Noisy (in std_ulogic_vector) – Noisy input signals
  • Filtered (out std_ulogic_vector) – Filtered output