filtering

extras_2008/filtering.vhdl

Description

This package implements general purpose digital filters.

Example usage

TODO

Subtypes

filtering.attenuation_factor

Attenuation gain from 0.0 to 1.0.

Components

fir_filter

component fir_filter is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Coefficients : in signed_array; --# {{data|Write port}} Data_valid : in std_ulogic; Data : in signed; Busy : out std_ulogic; --# {{Read port}} Result_valid : out std_ulogic; Result : out signed; In_use : in std_ulogic ); end component;

filtering.fir_filter

Finite Impulse Response filter.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Coefficients (in signed_array) – Filter tap coefficients
  • Data_valid (in std_ulogic) – Indicate when Data is valid
  • Data (in signed) – Data input to the filter
  • Busy (out std_ulogic) – Indicate when filter is ready to accept new data
  • Result_valid (out std_ulogic) – Indicates when a new filter result is valid
  • Result (out signed) – Filtered output
  • In_use (in std_ulogic) – Request to keep Result unchanged

lowpass_filter

component lowpass_filter is generic ( RESET_ACTIVE_LEVEL : std_ulogic; ALPHA : real; REGISTERED_MULTIPLY : boolean ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Data : in signed; Result : out signed ); end component;

filtering.lowpass_filter

First order lowpass filter. This filter operates in two modes. When REGISTERED_MULTIPLY is false the filter processes a new data sample on every clock cycle.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
  • ALPHA (real) – Alpha parameter computed with lowpass_alpha()
  • REGISTERED_MULTIPLY (boolean) – Control registration of internal mutiplier
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Data (in signed) – Data input to the filter
  • Result (out signed) – Filtered output

attenuate

component attenuate is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Gain : in signed; --# {{data|Write port}} Data_valid : in std_ulogic; Data : in signed; --# {{Read port}} Result_valid : out std_ulogic; Result : out signed ); end component;

filtering.attenuate

Scale samples by an attenuation factor.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Gain (in signed) – Attenuation factor
  • Data_valid (in std_ulogic) – Indicate when Data is valid
  • Data (in signed) – Data input to the filter
  • Result_valid (out std_ulogic) – Indicates when a new filter result is valid
  • Result (out signed) – Filtered output

sampler

component sampler is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|Write port}} Data_valid : in std_ulogic; Data : in std_ulogic; --# {{Read port}} Result_valid : out std_ulogic; Result : out signed ); end component;

filtering.sampler

Convert binary data into numeric samples.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Data_valid (in std_ulogic) – Indicate when Data is valid
  • Data (in std_ulogic) – Data input to the filter
  • Result_valid (out std_ulogic) – Indicates when a new filter result is valid
  • Result (out signed) – Filtered output

sample_and_hold

component sample_and_hold is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|Write port}} Data_valid : in std_ulogic; Data : in signed; Busy : out std_ulogic; --# {{Read port}} Result_valid : out std_ulogic; Result : out signed; In_use : in std_ulogic ); end component;

filtering.sample_and_hold

Capture and hold data samples.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Data_valid (in std_ulogic) – Indicate when Data is valid
  • Data (in signed) – Data input to the filter
  • Busy (out std_ulogic) – Indicate when filter is ready to accept new data
  • Result_valid (out std_ulogic) – Indicates when a new filter result is valid
  • Result (out signed) – Filtered output
  • In_use (in std_ulogic) – Request to keep Result unchanged

Subprograms

filtering.attenuation_gain (Factor : attenuation_factor; Size : positive) → signed
Convert attenuation factor into a signed factor
Parameters:
  • Factor (attenuation_factor) – Factor for gain value
  • Size (positive) – Number of bits in the result
Returns:

Signed value representing the Factor scaled to the range of Size.
filtering.lowpass_alpha (Tau : real; Sample_period : real) → real
Compute the alpha value for a lowpass filter
Parameters:
  • Tau (real) – Time constant
  • Sample_period (real) – Sample period of the filtered data
Returns:

Alpha constant passed to the lowpass_filter component.