timing_ops¶

Dependencies¶

Description¶

This is a package of functions to perform calculations on time and convert between different representations. The clock_gen() procedures can be used to create a clock signal for simulation.

A new physical type frequency is introduced and conversions between time, frequency, and real (time and frequency) are provided. Functions to convert from time in these three forms to integer clock_cycles are also included. The conversion from time to real uses an integer intermediate representation of time. It is designed to compensate for tools that use 64-bit time and 32-bit integers but only 31-bits of precision will be maintained in such cases.

For all conversion functions, real values of time are expressed in units of seconds and real frequencies are in 1/sec. e.g. 1 ns = 1.0e-9, 1 MHz = 1.0e6.

User defined physical types are limited to the range of integer. On 32-bit platforms frequency'high = (2**31)-1 Hz = 2.14 GHz. Real numbers must be used to represent higher frequencies.

The to_clock_cycles() functions can introduce rounding errors and produce a result that is different from what would be expected assuming infinite precision. The magnitude of any errors will depend on how close the converted time is to the clock period. To assist in controlling the errors, a time_rounding parameter is available on all forms of to_clock_cycles that use real as an intermediate type for the calculation. It is set by default to round up toward infinity in anticipation that these functions will most often be used to compute the minium number of cycles for a delay. You can override this behavior to either round down or maintain normal round to nearest for the conversion from real to clock_cycles.

To help detect the effect of rounding errors the time_duration() and report_time_precision() routines can be used in simulation to indicate deviation from the requested time span.

Xilinx note¶

The Xilinx version of timing_ops is needed for synthesis with Xilinx XST. The physical type frequency and any associated functions have been removed. The standard timing_ops package will work with Xilinx Vivado and most third party synthesizers so consider using it instead if XST is not being used.

Example usage¶

library extras; use extras.sizing.bit_size; use extras.timing_ops.all;

constant SYS_CLOCK_FREQ : frequency := 50 MHz;
constant COUNT_1US : clock_cycles
  := to_clock_cycles(1 us, SYS_CLOCK_FREQ);
signal   counter   : unsigned(bit_size(COUNT_1US)-1 downto 0);
...
counter <= to_unsigned(COUNT_1US, counter'length); -- initialize counter
report_time_precision("COUNT_1US", COUNT_1US, 1 us,
  time_duration(COUNT_1US, SYS_CLOCK_FREQ));

The value of the COUNT_1US constant will change to reflect any change in the system clock frequency and the size of the signal counter will now automatically adapt to guarantee it can represent the count for 1 us.

The clock_gen() procedure can be called from a process to generate a clock in simulation with the requested frequency or period and an optional duty cycle specification:

sys_clock_gen: process
begin
  clock_gen(sys_clock, stop_clock, SYS_CLOCK_FREQ);
  wait;
end process;

Types¶

timing_ops.frequency¶: Frequency physical type.

timing_ops.time_rounding¶: Rounding modes.

Subtypes¶

timing_ops.clock_cycles¶: Clock cycle count.

timing_ops.duty_cycle¶: Duty cycle ranging from 0 to 1.0.

Constants¶

timing_ops.TIME_ROUND_STYLE¶: Default rounding mode. Round to nearest.

Subprograms¶

timing_ops.resolution_limit() → delay_length¶

Get the current simulation time resolution.

Example:

variable min_time : time := resolution_limit;
...
wait for min_time;

timing_ops.to_real (Tval : time) → real¶

Convert time to real time.

Parameters:	Tval (time) – Time to convert
Returns:	Time converted to a real in units of seconds.

Example:

variable rtime : real;
rtime := to_real(now);

timing_ops.to_time (Rval : real) → time¶

Convert real time to time.

Parameters:	Rval (real) – Time to convert
Returns:	Real converted to time.

Example:

variable itime : time;
itime := to_time(1.0e-6);

timing_ops.to_period (Freq : frequency) → delay_length¶

Convert frequency to period.

Parameters:	Freq (frequency) – Frequency to convert
Returns:	Inverse of the frequency.

Example:

variable period : delay_length;
period := to_period(10 MHz);

timing_ops.to_period (Freq : real) → delay_length¶

Convert real frequency to period.

Parameters:	Freq (real) – Frequency to convert
Returns:	Inverse of the frequency.

Example:

variable period : delay_length;
period := to_period(10.0e6);

timing_ops.to_real (Freq : frequency) → real¶

Convert frequency to real frequency.

Parameters:	Freq (frequency) – Frequency to convert
Returns:	Real frequency.

Example:

variable rfreq : real;
rfreq := to_real(10 MHz);

timing_ops.to_frequency (Period : delay_length) → frequency¶

Convert period to frequency.

Parameters:	Period (delay_length) – Period to convert
Returns:	Inverse of the period.

Example:

variable freq : frequency;
freq := to_frequency(1 us);

timing_ops.to_frequency (Period : real) → frequency¶

Convert real period to frequency.

Parameters:	Period (real) – Period to convert
Returns:	Inverse of the period.

Example:

variable freq : frequency;
freq := to_frequency(1.0e-6);

timing_ops.to_clock_cycles (Secs : delay_length; Clock_freq : frequency; round_style : time_rounding := TIME_ROUND_STYLE) → clock_cycles¶

Compute clock cycles for the specified number of seconds using a clock frequency as the time base.

Parameters:	Secs (delay_length) – Time to convert to cycles Clock_freq (frequency) – Frequency of the clock round_style (time_rounding) – Optional rounding mode
Returns:	Time converted into integral cycles.

timing_ops.to_clock_cycles (Secs : delay_length; Clock_freq : real; round_style : time_rounding := TIME_ROUND_STYLE) → clock_cycles¶

Compute clock cycles for the specified number of seconds using a real clock frequency as the time base.

Parameters:	Secs (delay_length) – Time to convert to cycles Clock_freq (real) – Frequency of the clock round_style (time_rounding) – Optional rounding mode
Returns:	Time converted into integral cycles.

timing_ops.to_clock_cycles (Secs : real; Clock_freq : real; round_style : time_rounding := TIME_ROUND_STYLE) → clock_cycles¶

Compute clock cycles for the specified number of real seconds using a real clock frequency as the time base.

Parameters:	Secs (real) – Time to convert to cycles Clock_freq (real) – Frequency of the clock round_style (time_rounding) – Optional rounding mode
Returns:	Time converted into integral cycles.

timing_ops.to_clock_cycles (Secs : real; Clock_freq : frequency; round_style : time_rounding := TIME_ROUND_STYLE) → clock_cycles¶

Compute clock cycles for the specified number of real seconds using a clock frequency as the time base.

Parameters:	Secs (real) – Time to convert to cycles Clock_freq (frequency) – Frequency of the clock round_style (time_rounding) – Optional rounding mode
Returns:	Time converted into integral cycles.

timing_ops.to_clock_cycles (Secs : delay_length; Clock_period : delay_length) → clock_cycles¶

Compute clock cycles for the specified number of seconds using a clock period as the time base.

Parameters:	Secs (delay_length) – Time to convert to cycles Clock_period (delay_length) – Period of the clock
Returns:	Time converted into integral cycles.

timing_ops.to_clock_cycles (Secs : real; Clock_period : delay_length; round_style : time_rounding := TIME_ROUND_STYLE) → clock_cycles¶

Compute clock cycles for the specified number of real seconds using a clock period as the time base.

Parameters:	Secs (real) – Time to convert to cycles Clock_period (delay_length) – Period of the clock
Returns:	Time converted into integral cycles.

timing_ops.time_duration (Cycles : clock_cycles; Clock_freq : real) → delay_length¶

Calculate the time span represented by a number of clock cycles.

Parameters:	Cycles (clock_cycles) – Number of cycles to convert Clock_freq (real) – Frequency of the clock
Returns:	Cycles converted into time.

timing_ops.time_duration (Cycles : clock_cycles; Clock_period : delay_length) → delay_length¶

Calculate the time span represented by a number of clock cycles.

Parameters:	Cycles (clock_cycles) – Number of cycles to convert Clock_period (delay_length) – Period of the clock
Returns:	Cycles converted into time.

timing_ops.time_duration (Cycles : clock_cycles; Clock_freq : real) → real¶

Calculate the real time span represented by a number of clock cycles.

Parameters:	Cycles (clock_cycles) – Number of cycles to convert Clock_freq (real) – Frequency of the clock
Returns:	Cycles converted into real time.

timing_ops.report_time_precision (Identifier : in string; Cycles : in clock_cycles; Requested_secs : in real; Actual_secs : in real)¶

Report statement for checking difference between requested time value and the output of to_clock_cycles().

Parameters:	Identifier (in string) – User specified name included in report Cycles (in clock_cycles) – Output of to_clock_cycles() Requested_secs (in real) – Input passed to to_clock_cycles() Actual_secs (in real) – Output from time_duration()

timing_ops.report_time_precision (Identifier : in string; Cycles : in clock_cycles; Requested_secs : in time; Actual_secs : in time)¶

Report statement for checking difference between requested time value and the output of to_clock_cycles().

Parameters:	Identifier (in string) – User specified name included in report Cycles (in clock_cycles) – Output of to_clock_cycles() Requested_secs (in time) – Input passed to to_clock_cycles() Actual_secs (in time) – Output from time_duration()

timing_ops.clock_gen (Clock : out std_ulogic; Stop_clock : in boolean; Clock_freq : in frequency; Duty : in duty_cycle := 0.5)¶

Generate clock waveform for simulation only.

Parameters:	Clock (out std_ulogic) – Generated clock signal Stop_clock (in boolean) – Control signal that exits procedure when true Clock_freq (in frequency) – Frequency of the generated clock Duty (in duty_cycle) – Optional duty cycle of the generated clock (0.0 to 1.0)

timing_ops.clock_gen (Clock : out std_ulogic; Stop_clock : in boolean; Clock_period : in delay_length; Duty : in duty_cycle := 0.5)¶

Generate clock waveform for simulation only.

Parameters:	Clock (out std_ulogic) – Generated clock signal Stop_clock (in boolean) – Control signal that exits procedure when true Clock_period (in delay_length) – Period of the generated clock Duty (in duty_cycle) – Optional duty cycle of the generated clock (0.0 to 1.0)

timing_ops¶

Dependencies¶

Description¶

Xilinx note¶

Example usage¶

Types¶

Subtypes¶

Constants¶

Subprograms¶

Related Topics

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