oscillator

extras/oscillator.vhdl

Dependencies

ddfs, cordic, sizing, timing_ops

Description

This package provides a set of components that implement arbitrary sinusoidal frequency generators. They come in two variants. One generates a fixed frequency that is specified at elaboration time as a generic parameter. The other generates a dynamic frequency that can be altered at run time. Each of these oscillator variants comes in two versions. One is based around a pipelined CORDIC unit that produces new valid output on every clock cycle. The other uses a more compact sequential CORDIC implementation that takes multiple clock cycles to produce each output.

All oscillators output sine, cosine, the current phase angle, and a generated clock at the target frequency.

Example usage

TODO

Components

fixed_oscillator

component fixed_oscillator is generic ( SYS_CLOCK_FREQ : frequency; OUTPUT_FREQ : frequency; TOLERANCE : real; SIZE : positive; ITERATIONS : positive; MAGNITUDE : real; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Load_phase : in std_ulogic; New_phase : in unsigned; --# {{data|}} Sin : out signed(SIZE-1 downto 0); Cos : out signed(SIZE-1 downto 0); Angle : out signed(SIZE-1 downto 0); Synth_clock : out std_ulogic ); end component;

oscillator.fixed_oscillator

Oscillator with a fixed frequency output. Samples are generated on every clock cycle.

Generics:
  • SYS_CLOCK_FREQ (frequency) – System clock frequency
  • OUTPUT_FREQ (frequency) – Generated frequency
  • TOLERANCE (real) – Error tolerance
  • SIZE (positive) – Width of operands
  • ITERATIONS (positive) – Number of iterations for CORDIC algorithm
  • MAGNITUDE (real) – Scale factor for Sin and Cos
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Load_phase (in std_ulogic) – Load a new phase angle
  • New_phase (in unsigned) – Phase angle to load
  • Sin (out signed(SIZE-1 downto 0)) – Sine output
  • Cos (out signed(SIZE-1 downto 0)) – Cosine output
  • Angle (out signed(SIZE-1 downto 0)) – Phase angle in brads
  • Synth_clock (out std_ulogic) – Generated clock

fixed_oscillator_sequential

component fixed_oscillator_sequential is generic ( SYS_CLOCK_FREQ : frequency; OUTPUT_FREQ : frequency; TOLERANCE : real; SIZE : positive; ITERATIONS : positive; MAGNITUDE : real; CAPTURE_RESULT : boolean; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Load_phase : in std_ulogic; New_phase : in unsigned; Result_valid : out std_ulogic; --# {{data|}} Sin : out signed(SIZE-1 downto 0); Cos : out signed(SIZE-1 downto 0); Angle : out signed(SIZE-1 downto 0); Synth_clock : out std_ulogic ); end component;

oscillator.fixed_oscillator_sequential

Oscillator with a fixed frequency output. Samples are generated on after every ITERATIONS clock cycles.

Generics:
  • SYS_CLOCK_FREQ (frequency) – System clock frequency
  • OUTPUT_FREQ (frequency) – Generated frequency
  • TOLERANCE (real) – Error tolerance
  • SIZE (positive) – Width of operands
  • ITERATIONS (positive) – Number of iterations for CORDIC algorithm
  • MAGNITUDE (real) – Scale factor for Sin and Cos
  • CAPTURE_RESULT (boolean) – Register outputs when valid
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Load_phase (in std_ulogic) – Load a new phase angle
  • New_phase (in unsigned) – Phase angle to load
  • Result_valid (out std_ulogic) – New samples are ready
  • Sin (out signed(SIZE-1 downto 0)) – Sine output
  • Cos (out signed(SIZE-1 downto 0)) – Cosine output
  • Angle (out signed(SIZE-1 downto 0)) – Phase angle in brads
  • Synth_clock (out std_ulogic) – Generated clock

dynamic_oscillator

component dynamic_oscillator is generic ( SYS_CLOCK_FREQ : real; MIN_TGT_FREQ : natural; TOLERANCE : real; SIZE : natural; ITERATIONS : positive; MAGNITUDE : real; FREQ_SCALE : natural; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Load_phase : in std_ulogic; New_phase : in unsigned; Dyn_freq : in unsigned; --# {{data|}} Sin : out signed(SIZE-1 downto 0); Cos : out signed(SIZE-1 downto 0); Angle : out signed(SIZE-1 downto 0); Synth_clock : out std_ulogic ); end component;

oscillator.dynamic_oscillator
Generics:
  • SYS_CLOCK_FREQ (real) – System clock frequency
  • MIN_TGT_FREQ (natural) – Lowest supported output frequency
  • TOLERANCE (real) – Error tolerance
  • SIZE (natural) – Width of operands
  • ITERATIONS (positive) – Number of iterations for CORDIC algorithm
  • MAGNITUDE (real) – Scale factor for Sin and Cos magnitude
  • FREQ_SCALE (natural) – Scale factor for target frequency
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Load_phase (in std_ulogic) – Load a new phase angle
  • New_phase (in unsigned) – Phase angle to load
  • Dyn_freq (in unsigned) – Dynamic frequency in FIXME
  • Sin (out signed(SIZE-1 downto 0)) – Sine output
  • Cos (out signed(SIZE-1 downto 0)) – Cosine output
  • Angle (out signed(SIZE-1 downto 0)) – Phase angle in brads
  • Synth_clock (out std_ulogic) – Generated clock

dynamic_oscillator_sequential

component dynamic_oscillator_sequential is generic ( SYS_CLOCK_FREQ : real; MIN_TGT_FREQ : natural; TOLERANCE : real; SIZE : natural; ITERATIONS : positive; MAGNITUDE : real; FREQ_SCALE : natural; CAPTURE_RESULT : boolean; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Load_phase : in std_ulogic; New_phase : in unsigned; Dyn_freq : in unsigned; --# {{data|}} Sin : out signed(SIZE-1 downto 0); Cos : out signed(SIZE-1 downto 0); Angle : out signed(SIZE-1 downto 0); Synth_clock : out std_ulogic ); end component;

oscillator.dynamic_oscillator_sequential
Generics:
  • SYS_CLOCK_FREQ (real) – System clock frequency
  • MIN_TGT_FREQ (natural) – Lowest supported output frequency
  • TOLERANCE (real) – Error tolerance
  • SIZE (natural) – Width of operands
  • ITERATIONS (positive) – Number of iterations for CORDIC algorithm
  • MAGNITUDE (real) – Scale factor for Sin and Cos magnitude
  • FREQ_SCALE (natural) – Scale factor for target frequency
  • CAPTURE_RESULT (boolean) – Register outputs when valid
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Load_phase (in std_ulogic) – Load a new phase angle
  • New_phase (in unsigned) – Phase angle to load
  • Dyn_freq (in unsigned) – Dynamic frequency in FIXME
  • Sin (out signed(SIZE-1 downto 0)) – Sine output
  • Cos (out signed(SIZE-1 downto 0)) – Cosine output
  • Angle (out signed(SIZE-1 downto 0)) – Phase angle in brads
  • Synth_clock (out std_ulogic) – Generated clock