lcar_ops

extras/lcar_ops.vhdl

Dependencies

None

Description

This package provides a component that implements the Wolfram Linear Cellular Automata Register (LCAR) as described in “Statistical Mechanics of Cellular Automata”, Wolfram 1983. The LCAR implemented in wolfram_lcar uses rules 90 and 150 for each cell as defined by an input Rule_map where a ‘0’ indicates rule 90 and ‘1’ indicates rule 150 for the corresponding cell in the State register.

The LCAR using rules 90 and 150 can produce output equivalent to maximal length LFSRs but with the advantage of less correlation between bits of the state register. This makes the LCAR more suitable for pseudo-random number generation. The predefined LCAR_* constants provide rule maps for maximal length sequences.

For basic pseudo-random state generation it is sufficient to tie the Left_in and Right_in inputs to ‘0’.

library extras;
use extras.lcar_ops.all;

constant WIDTH : positive := 8;
constant rule : std_ulogic_vector(WIDTH-1 downto 0) := lcar_rule(WIDTH);
variable state : std_ulogic_vector(WIDTH-1 downto 0) := (others => '1');
...
-- Basic usage with default '0's shifting in from ends
state := next_wolfram_lcar(state, rule);

library extras;
use extras.lcar_ops.all;

constant WIDTH : positive := 8;
constant rule  : std_ulogic_vector(WIDTH-1 downto 0) := lcar_rule(WIDTH);
signal   state : std_ulogic_vector(WIDTH-1 downto 0) := (others => '1');
...

wl: wolfram_lcar
  port map (
    Clock => clock,
    Reset => reset,
    Enable => enable,

    Rule_map => rule
    Left_in => '0',
    Right_in => '0',

    State => state
  );

Components

wolfram_lcar

component wolfram_lcar is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; Enable : in std_ulogic; --# {{control|}} Rule_map : in std_ulogic_vector; --# {{data|}} Left_in : in std_ulogic; Right_in : in std_ulogic; State : out std_ulogic_vector ); end component;

lcar_ops.wolfram_lcar

General purpose implementation of a rule 150/90 LCAR.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Enable (in std_ulogic) – Synchronous enable
  • Rule_map (in std_ulogic_vector) – Rules for each cell ‘1’ -> 150, ‘0’ -> 90
  • Left_in (in std_ulogic) – Left side input to LCAR
  • Right_in (in std_ulogic) – Right side input to LCAR
  • State (out std_ulogic_vector) – The state of each cell

Subprograms

lcar_ops.next_wolfram_lcar (State : std_ulogic_vector; Rule_map : std_ulogic_vector; Left_in : std_ulogic := '0'; Right_in : std_ulogic := '0') → std_ulogic_vector
Determine the next state of the LCAR defined by the Rule_map.
Parameters:
  • State (std_ulogic_vector) – Current state of the LCAR cells
  • Rule_map (std_ulogic_vector) – Rules for each cell; ‘1’ -> 150, ‘0’ -> 90
  • Left_in (std_ulogic) – Left side input to LCAR
  • Right_in (std_ulogic) – Right side input to LCAR
Returns:

Next iteration of the LCAR rules which becomes the new state
lcar_ops.lcar_rule (Size : positive) → std_ulogic_vector
Lookup a predefined rule set from the table.
Parameters:
  • Size (positive) – Number of LCAR cells
Returns:

Rule map for a maximal length sequence.