interrupt_ctl

extras/interrupt_ctl.vhdl

Dependencies

None

Description

This package provides a general purpose interrupt controller that handles the management of multiple interrupt sources. It uses unconstrained arrays to specify the interrupt vector signals. It can thus be sized as needed to suit required number of interrupts.

The priority of the interrupts is fixed with the lowest index having the highest priority. You can use ascending or descending ranges for the control vectors. Multiple pending interrupts are serviced from highest to lowest priority. If a higher priority interrupt arrives when a lower priority interrupt is currently in service, the higher priority interrupt takes effect after the lower interrupt is acknowledged. If you disable a pending interrupt with its mask it will not return after reenabling the mask bit until the next interrupt arrives.

Example usage

-- Create an 8-bit interrupt controller
signal int_mask, int_request, pending_int, current_int :
      std_ulogic_vector(7 downto 0);
...
-- Disable interrupts 5, 6, and 7
int_mask <= (7 downto 5 => '0', others => '1');
ic: interrupt_ctl
 port map (
   Clock => clock,
   Reset => reset,

   Int_mask    => int_mask,     -- Mask to enable/disable interrupts
   Int_request => int_request,  -- Interrupt sources
   Pending     => pending_int,  -- Current set of pending interrupts
   Current     => current_int,  -- Vector identifying which interrupt is active

   Interrupt     => interrupt,     -- Signal when an interrupt is ping
   Acknowledge   => interrupt_ack, -- Acknowledge the interrupt has been serviced
   Clear_pending => clear_pending  -- Optional control to clear all
 );

-- Assemble interrupt sources into a request vector
int_request <= (
 0 => source1, -- Highest priority
 1 => source2,
 2 => source3,
 3 => source4, -- Lowest priority
 others => '0'); -- The remaining sources are unused

Components

interrupt_ctl

component interrupt_ctl is generic ( RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Int_mask : in std_ulogic_vector; Int_request : in std_ulogic_vector; Pending : out std_ulogic_vector; Current : out std_ulogic_vector; Interrupt : out std_ulogic; Acknowledge : in std_ulogic; Clear_pending : in std_ulogic ); end component;

interrupt_ctl_pkg.interrupt_ctl

Priority interrupt controller.

Generics:
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Int_mask (in std_ulogic_vector) – Set bits correspond to active interrupts
  • Int_request (in std_ulogic_vector) – Controls used to activate new interrupts
  • Pending (out std_ulogic_vector) – Set bits indicate which interrupts are pending
  • Current (out std_ulogic_vector) – Single set bit for the active interrupt
  • Interrupt (out std_ulogic) – Flag indicating when an interrupt is pending
  • Acknowledge (in std_ulogic) – Clear the active interupt
  • Clear_pending (in std_ulogic) – Clear all pending interrupts