arithmetic

extras/arithmetic.vhdl

Dependencies

pipelining

Description

This is an implementation of general purpose pipelined adder. It can be configured for any number of stages and bit widths. The adder is divided into a number of slices each of which is a conventional adder. The maximum carry chain length is reduced to ceil(bit-length / slices).

--[]-[]-[Slice]--> Sum_3
--[]-[Slice]-[]--> Sum_2
--[Slice]-[]-[]--> Sum_1

Example usage

-- 16-bit adder partitioned into 4 4-bit slices
signal A, B, Sum : unsigned(15 downto 0);

pa: pipelined_adder
  generic map (
    SLICES => 4,
    CONST_B_INPUT => false,
    RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
  )
  port map (
    Clock => clock,
    Reset => reset,

    A => A,
    B => B,

    Sum => Sum
  );

Components

pipelined_adder

component pipelined_adder is generic ( SLICES : positive; CONST_B_INPUT : boolean; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} A : in unsigned; B : in unsigned; Sum : out unsigned ); end component;

arithmetic.pipelined_adder

Variable size pipelined adder.

Generics:
  • SLICES (positive) – Number of pipeline stages
  • CONST_B_INPUT (boolean) – Optimize when the B input is constant
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • A (in unsigned) – Addend A
  • B (in unsigned) – Addend B
  • Sum (out unsigned) – Result sum of A and B