synchronizing

extras/synchronizing.vhdl

Dependencies

None

Description

This package provides a number of synchronizer components for managing data transmission between clock domains. There are three entities provided:

  • bit_synchronizer – Suitable for synchronizing individual bit-wide signals
  • reset_synchronizer – A special synchronizer for generating asyncronous resets that are synchronously released
  • handshake_synchronizer – A synchronizer using the four-phase protocol to transfer vectors between domains

bit_synchronizer and reset_synchronizer have a configurable number of stages with a default of 2.

If you need to synchronize a vector of bits together you should use the handshake_synchronizer component. If you generate an array of bit_synchronizer components instead, there is a risk that some bits will take longer than others and invalid values will appear at the outputs. This is particularly problematic if the vector represents a numeric value. bit_synchronizer can be used safely in an array only if you know the input signal comes from an isochronous domain (same period, different phase).

Synthesis

Vendor specific synthesis attributes have been included to help prevent undesirable results. It is important to know that, ideally, synchronizing flip-flops should be placed as close together as possible. It is also desirable to have the first stage flip-flop incorporated into the input buffer to minimize input delay. Because of this these components do not have attributes to guide relative placement of flip-flops to make them contiguous. Instead you should apply timing constraints to the components that will force the synthesizer into using an optimal placement.

Components

bit_synchronizer

component bit_synchronizer is generic ( STAGES : natural; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Bit_in : in std_ulogic; Sync : out std_ulogic ); end component;

synchronizing.bit_synchronizer

A basic synchronizer with a configurable number of stages. The Sync output is synchronized to the Clock domain.

Generics:
  • STAGES (natural) – Number of flip-flops in the synchronizer
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Bit_in (in std_ulogic) – Unsynchronized signal
  • Sync (out std_ulogic) – Synchronized to Clock’s domain

reset_synchronizer

component reset_synchronizer is generic ( STAGES : natural; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{data|}} Sync_reset : out std_ulogic ); end component;

synchronizing.reset_synchronizer

Synchronizer for generating a synchronized reset. The deactivating edge transition for the Sync_reset output is synchronized to the Clock domain. Its activating edge remains asynchronous.

Generics:
  • STAGES (natural) – Number of flip-flops in the synchronizer
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Sync_reset (out std_ulogic) – Synchronized reset

handshake_synchronizer

component handshake_synchronizer is generic ( STAGES : natural; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock_tx : in std_ulogic; Reset_tx : in std_ulogic; Clock_rx : in std_ulogic; Reset_rx : in std_ulogic; --# {{data|Send port}} Tx_data : in std_ulogic_vector; Send_data : in std_ulogic; Sending : out std_ulogic; Data_sent : out std_ulogic; --# {{Receive port}} Rx_data : out std_ulogic_vector; New_data : out std_ulogic ); end component;

synchronizing.handshake_synchronizer

A handshaking synchronizer for sending an array between clock domains. This uses the four-phase handshake protocol.

Generics:
  • STAGES (natural) – Number of flip-flops in the synchronizer
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock_tx (in std_ulogic) – Transmitting domain clock
  • Reset_tx (in std_ulogic) – Asynchronous reset for Clock_tx
  • Clock_rx (in std_ulogic) – Receiving domain clock
  • Reset_rx (in std_ulogic) – Asynchronous reset for Clock_rx
  • Tx_data (in std_ulogic_vector) – Data to send
  • Send_data (in std_ulogic) – Control signal to send new data
  • Sending (out std_ulogic) – Active while TX is in process
  • Data_sent (out std_ulogic) – Flag to indicate TX completion
  • Rx_data (out std_ulogic_vector) – Data received in clock_rx domain
  • New_data (out std_ulogic) – Flag to indicate new data