memory

extras/memory.vhdl

Dependencies

None

Description

This package provides general purpose components for inferred RAM and ROM. These memories share a SYNC_READ generic which will optionally generate synchronous or asynchronous read ports for each instance. On Xilinx devices asynchronous read forces the synthesis of distributed RAM using LUTs rather than BRAMs. When SYNC_READ is false the Read enable input is unused and the read port clock can be tied to ‘0’.

The ROM component gets its contents using synthesizable file IO to read a list of binary or hex values.

Example usage

Create a 256-byte ROM with contents supplied by the binary image file “rom.img”:

r: rom
  generic map (
    ROM_FILE => "rom.img",
    FORMAT => BINARY_TEXT,
    MEM_SIZE => 256
  )
  port map (
    Clock => clock,
    Re => re,
    Addr => addr,
    Data => data
  );

Types

memory.rom_format

Data file format. Either binary or ASCII hex.

Components

dual_port_ram

memory.dual_port_ram

A dual-ported RAM supporting writes and reads from separate clock domains.

Generics:

• MEM_SIZE (positive) – Number or words in memory
• SYNC_READ (boolean) – Register outputs of read port memory

Port:

• Wr_clock (in std_ulogic) – Write port clock
• We (in std_ulogic) – Write enable
• Wr_addr (in natural) – Write port address
• Wr_data (in std_ulogic_vector) – Write port data
• Rd_clock (in std_ulogic) – Read port clock
• Re (in std_ulogic) – Read enable
• Rd_addr (in natural) – Read port address
• Rd_data (out std_ulogic_vector) – Read port data

rom

memory.rom

A synthesizable ROM using a file to specify the contents.

Generics:

• ROM_FILE (string) – Name of file with ROM data
• FORMAT (rom_format) – File encoding
• MEM_SIZE (positive) – Number or words in memory
• SYNC_READ (boolean) – Register outputs of read port memory

Port:

• Clock (in std_ulogic) – System clock
• Re (in std_ulogic) – Read enable
• Addr (in natural) – Read address
• Data (out std_ulogic_vector) – Data at current address