bit_ops

extras/bit_ops.vhdl

Dependencies

sizing

Description

This package provides components that count the number of set bits in a vector. Multiple implementations are available with different performance characteristics.

Example usage

signal value : unsigned(11 downto 0);
signal ones_count : unsigned(bit_size(value'length)-1 downto 0);

-- Basic combinational circuit:
basic: count_ones
  port map (
    Value => value,
    Ones_count => ones_count
  );

-- Chunked combinational circuit:
basic: count_ones_chunked
  generic map (
    TABLE_BITS => 4 -- Constant table with 16 entries
  )
  port map (
    Value => value,
    Ones_count => ones_count
  );

-- Chunked sequential circuit:
basic: count_ones_chunked
  generic map (
    TABLE_BITS => 4 -- Constant table with 16 entries
  )
  port map (
    Clock => clock,
    Reset => reset,

    Start => start,
    Busy => busy,
    Done  => done,

    Value => value,
    Ones_count => ones_count
  );

Types

bit_ops.natural_vector

Vector of natural numbers.

Components

count_ones

component count_ones is port ( --# {{data|}} Value : in unsigned; Ones_count : out unsigned ); end component;

bit_ops.count_ones

Count the number of set bits in a vector.

Port:
  • Value (in unsigned) – Vector to count set bits
  • Ones_count (out unsigned) – Number of set bits in Value

count_ones_chunked

component count_ones_chunked is generic ( TABLE_BITS : positive ); port ( --# {{data|}} Value : in unsigned; Ones_count : out unsigned ); end component;

bit_ops.count_ones_chunked

Count the number of set bits in a vector with a reduced constant table.

Generics:
  • TABLE_BITS (positive) – Number of bits for constant table
Port:
  • Value (in unsigned) – Vector to count set bits
  • Ones_count (out unsigned) – Number of set bits in Value

count_ones_sequential

component count_ones_sequential is generic ( TABLE_BITS : positive; RESET_ACTIVE_LEVEL : std_ulogic ); port ( --# {{clocks|}} Clock : in std_ulogic; Reset : in std_ulogic; --# {{control|}} Start : in std_ulogic; Busy : out std_ulogic; Done : out std_ulogic; --# {{data|}} Value : in unsigned; Ones_count : out unsigned ); end component;

bit_ops.count_ones_sequential

Count the number of set bits in a vector with a reduced constant table.

Generics:
  • TABLE_BITS (positive) – Number of bits for constant table
  • RESET_ACTIVE_LEVEL (std_ulogic) – Asynch. reset control level
Port:
  • Clock (in std_ulogic) – System clock
  • Reset (in std_ulogic) – Asynchronous reset
  • Start (in std_ulogic) – Start counting
  • Busy (out std_ulogic) – Count is in progress
  • Done (out std_ulogic) – Count is done
  • Value (in unsigned) – Vector to count set bits
  • Ones_count (out unsigned) – Number of set bits in Value

Subprograms

bit_ops.gen_count_ones_table (Size : positive) → natural_vector
Create a precomputed table of bit counts.
Parameters:
  • Size (positive) – Number of bits in vector
Returns:

Array of bit count values with 2**Size entries.